1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Description of the Related Art
An integrated circuit has been developed, which uses a semiconductor substrate called a silicon-on-insulator (hereinafter also referred to as an SOI) that has a thin single crystal semiconductor layer on an insulating surface, instead of a silicon wafer that is manufactured by thinly slicing an ingot of a single crystal semiconductor. The integrated circuit using an SOI substrate has attracted attention as an integrated circuit which reduces parasitic capacitance between a drain of a transistor and the substrate and improves the performance of a semiconductor integrated circuit.
As a method for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (for example, see Patent Document 1). The hydrogen ion implantation separation method is a method in which hydrogen ions are implanted into a silicon wafer to form an embrittled region at a predetermined depth from a surface of the silicon wafer, the silicon wafer is split at the embrittled region, and a thin silicon layer is bonded to another silicon wafer.
In a CMOS technique, an NMOS and a PMOS are mainly formed with use of a silicon wafer having a (100) plane orientation. This (100) plane has high electron mobility, and is a crystal plane suitable for an NMOS; however, a (110) plane has high hole mobility, so the (100) plane is not a crystal plane suitable for a PMOS as compared with the (110) plane. In contrast, the (110) plane is a crystal plane suitable for a PMOS, but has lower electron mobility than the (100) plane; therefore, the (110) plane is not a crystal plane suitable for an NMOS.
In view of the above, in order to utilize both electron mobility of an NMOS and hole mobility of a PMOS, a semiconductor device in which a PMOS formed on a silicon wafer that has a (110) plane and an NMOS formed on a silicon layer that has a (100) plane formed on the silicon wafer having a (110) plane are provided is known (for example, see Patent Document 2).
[Reference]
    [Patent Document]    [Patent Document 1] Japanese Published Patent Application No. 2000-124092    [Patent Document 2] Japanese Published Patent Application No. 2006-229047